Field effect transistor (FET) technology is well suited for high density, low power circuits. Increased emphasis has also been placed on the FET technology for fabricating large scale integration circuits as such technology can provide complex logic functions and large memories with high yields. FET structures are fabricated using P-channel field effect transistors (PMOS) and N-channel transistors (NMOS). PMOS and NMOS transistor devices have been combined to form complementary metal oxide semiconductor (CMOS) circuits which provide improved performance over that of the individual devices.
As the degree of circuit complexity and integration increases, the speed of the FET circuits can become degraded due to capacitive loading. This is especially noticeable with FET output devices which must produce appreciable drive currents to other circuits. One approach for improving the drive capabilities of an FET device is to increase the width of its conduction channel. However, the shortcoming attendant with this approach is that the device requires more area, thereby hampering the ability to place a larger number of devices into a smaller area. Another approach for improving the speed characteristics of circuits using FET devices is to use bipolar transistors for the driving elements. Bipolar transistors are characterized by a high transconductance, thereby producing excellent drive capabilities for capacitive loads, thus ensuring high gain and fast signal rise times for the driving signals.
The integration of bipolar devices with FET devices to enhance the speed characteristics of a circuit is well known in the art. The traditional steps in fabricating the base, emitter and collector features of a bipolar transistor are different from the steps in fabricating the source, drain and gate features of a CMOS device. As a result, when it is desired to integrate a bipolar device with a CMOS circuit, separate fabrication steps are necessary to form the bipolar device and the CMOS device. Conventionally, there is minimal commonality between the bipolar and CMOS fabrication processes. It can be appreciated that with these approaches, the advantages of an integrated bipolar and CMOS device were realized, but at the cost of a more complicated fabrication process with many steps. When a semiconductor fabrication process is modified with additional steps, the yield of the resultant product can be expected to decrease.
While more recent developments have brought the processing of the bipolar devices and the CMOS devices into closer correspondence, there is a need for an improved bipolar/CMOS process which more fully integrates the process steps, as well as the devices. There is also a need for a bipolar transistor layout which is compatible with the design and fabrication of MOS transistor circuits.